As is known, a microprogrammable device is an electronic device comprising: a processor; a code memory storing a software and/or firmware code comprising a set of instructions to be executed; and a data memory storing values of variables employed in executing the code.
More specifically, when operating, the microprogrammable device executes the code, i.e. the instructions, stored in the code memory.
When executing the code, the microprogrammable device may often find itself in a wait state with a number of possible exits, each depending on the occurrence of a respective condition.
One example of a wait state in which a microprogrammable device remains with constant exits for a certain length of time is represented by the on and off phases of a chopper operation.
More specifically, the microprogrammable device may “exit” the on (or off) phase when it detects, for example, one of the following conditions: a current or time limit is reached and it is necessary to switch to the complementary off (or on) phase; a time limit is reached and it is necessary to change macrophase; or a control pin of the microprogrammable device changes state and it is necessary to interrupt execution of the chopper operation.
To exit the wait state, the microprogrammable device therefore cyclically and continuously checks each individual condition.
More specifically, once the microprogrammable device has detected a given condition, it executes an instruction corresponding to that given condition.
In other words, execution of the code is “directed” according to the condition detected by the microprogrammable device.
In known microprogrammable devices, wait states of the above type are implemented by continuously and cyclically executing a set of instructions, each designed to check a corresponding condition.
By way of example, FIG. 1 shows a flow chart of an instruction execution logic of a known microprogrammable device in the case of a three-exit wait state.
More specifically, the instruction execution logic, indicated by 10 in the FIG. 1, comprises executing: a first instruction 11; a second instruction 12, after the execution of which the microprogrammable device enters into a wait state; a first check 13 of a first wait state exit condition; a third instruction 19, if the first wait state exit condition has been detected during the first check 13; a second check 14 of a second wait state exit condition, if the first wait state exit condition has not been detected during the first check 13; a fourth instruction 18, if the second wait state exit condition has been detected during the second check 14; a third check 15 of a third wait state exit condition, if the second wait state exit condition has not been detected during the second check 14; and a fifth instruction 17, if the third wait state exit condition has been detected during the third check 15.
Moreover, as shown in FIG. 1, if the third wait state exit condition has not been detected during the third check 15, the instruction execution logic 10 comprises repeating 16 the first check 13.
In known microprogrammable devices, each instruction is executed in a corresponding instruction cycle.
Moreover, each time an instruction is executed, a program counter, indicating the code memory address of the next instruction to be executed, is updated.
For example, in the FIG. 1 case, if during the first check 13 the first wait state exit condition is detected, the program counter is updated so as to address the third instruction 19 as the next one to be executed. Conversely, the program counter is updated so as to address the second check 14.
The Applicant, however, has observed that, in known wait state implementations, the time interval between the occurrence of a condition and execution of the corresponding instruction varies, i.e. is affected by a sort of jitter.
The length of the time interval, in fact, depends on the point at which the execution of the code is when the condition occurs.
For a clearer understanding of the problem, FIG. 2 shows three examples, indicated by 21, 22 and 23, respectively, of instructions executed in accordance with the instruction execution logic 10 in FIG. 1.
In detail, in the first example 21, the second wait state exit condition occurs simultaneously with an execution of the second check 14, so is therefore detected immediately, and the fourth instruction 18 is executed at the next instruction cycle.
In the first example 21, the time interval between occurrence of the second wait state exit condition and execution of the corresponding instruction, i.e. the fourth instruction 18, is therefore of one instruction cycle.
In the second example 22, on the other hand, the second wait state exit condition occurs simultaneously with an execution of the first check 13, so is therefore detected at the following instruction cycle when the second check 14 is executed, while the fourth instruction 18 is executed yet another instruction cycle later.
In the second example 22, the time interval between occurrence of the second wait state exit condition and execution of the fourth instruction 18 is therefore of two instruction cycles.
Finally, in the third example 23, the second wait state exit condition occurs simultaneously with an execution of the third check 15, so is therefore detected after three instruction cycles when the second check 14 is again executed, while the fourth instruction 18 is executed yet another instruction cycle later.
In the third example 23, the time interval between occurrence of the second condition and execution of the fourth instruction 18, is therefore of four instruction cycles.
Therefore, as stated, and as shown in the examples 21, 22 and 23, the time interval between occurrence of a wait state exit condition and execution of the corresponding instruction does not have a fixed length, i.e. is affected by jitter.